The present invention relates to integrated circuit testers for testing IC-chips (integrated circuit chips). More particularly, the present invention relates to integrated circuit testers which include a fail-safe mechanism for moving an IC-chip between an initial position where the IC-chip is inserted into the tester and a test position where the IC-chip is actually tested.
Typically, a single IC-chip contains more than one-hundred-thousand transistors. Thus, a manufacturer of IC-chips must test their IC-chips to ensure that they operate properly before they are sold to a customer. Conventionally, this testing is accomplished as follows.
Initially, one group of IC-chips that are to be tested are placed in respective sockets that are mounted on several printed circuit boards. Each printed circuit board has edge connectors on one edge of the board; and those connectors carry test signals, as well as DC electrical power, for the IC-chips that are in the sockets.
After the IC-chips are placed in the sockets, the printed circuit boards are inserted into fixed slots in an electromechanical apparatus where the chip testing occurs. As each printed circuit board is inserted into a slot, the edge connectors on the board plug into mating connectors that are provided in the slot.
Usually, several printed circuit boards are held in the slots, spaced-apart from each other, in a horizontal row. Alternatively, several printed circuit boards can be held in the slots, spaced-apart from each other, in a vertical column.
Multiple signal lines are provided in the IC-chip testing apparatus which extend from the connectors in the slots to a test signal controller. This controller tests the IC-chips by sending them test signals and receiving responses from them. Also, electrical power lines are provided in the IC-chip testing apparatus which extend from the connectors in the slots to one or more power supplies.
Often it is desirable to perform a xe2x80x9cburn-inxe2x80x9d test wherein the IC-chips are held at a high temperature while they are tested. In the prior art, that was done by enclosing the IC-chip testing apparatus in an oven and providing fans in the enclosure which circulate hot air past the IC-chips while they are tested.
However, one drawback with the above prior art testing apparatus is that the temperature at which the IC-chips are tested cannot be regulated accurately. This inaccuracy is caused, in part, by variations in the temperature and velocity of the air which flows past each of the IC-chips. Also, the inaccuracy is caused by variations in power dissipation which occurs within the IC-chips while they are being tested, and this problem gets worse as the magnitude of the power variations increase.
Further, another drawback with the above prior art IC-chip testing apparatus is that due to the row/column arrangement of the printed circuit boards, a large distance inherently exists between the IC-chips that are tested and the power supplies for those IC-chips. Due to those large distances, parasitic resistances, parasitic inductances and parasitic capacitances are inherently large; and thus, the more difficult it becomes to keep the IC-chip voltages constant while IC-chip power dissipation changes rapidly.
To avoid the above technical problems, a novel architecture for an IC-chip testing apparatus has been developed wherein an IC-chip holding subassembly, a power converter subassembly, and a temperature regulating subassembly are squeezed together in multiple sets by respective pressing mechanisms. One major benefit which is achieved with this architecture is that by pressing the temperature regulating subassembly against the IC-chip holding subassembly, heat can be added/removed from the IC-chips by conduction; and thus the temperature of the IC-chips can be regulated accurately. Another major benefit which is achieved with this architecture is that by pressing the power converter subassembly against the IC-chip holding subassembly, the distance between the IC-chips and their power supplies is made small; and, consequently, the IC-chip voltages can easily be kept constant while the IC-chip power dissipation changes.
One preferred embodiment of the above IC-chip testing apparatus is disclosed in U.S. patent application Ser. No. 09/511,789 which is assigned to the assignee of the present invention. In that IC-chip testing apparatus, a motorized mechanism is provided which moves the IC-chip holding subassembly between an xe2x80x9cinitialxe2x80x9d position (also called the xe2x80x9copenxe2x80x9d position) and a xe2x80x9ctestxe2x80x9d position (also called the xe2x80x9cclosedxe2x80x9d position). In the initial or open position, the IC-chip holding subassembly is spaced-apart from the power converter subassembly and the temperature regulating subassembly; and that enables the IC-chip holding subassembly to be inserted into/removed from the IC-chip testing apparatus. In the test or closed position, the IC-chip holding subassembly is squeezed between the power converter subassembly and the temperature regulating subassembly; and there, the IC-chips are actually tested.
To operate the motorized mechanism, an electronic control circuit can be included which senses when the IC-chip holding subassembly is at the initial position, or at the test position; and which automatically stops the motor in response. However, the present inventors have found that damage to the IC-chip testing apparatus can occur even when this electronic control circuit is included. For example, the sensors which are provided for sensing the initial position and test position of the IC-chip holding subassembly can fail; or, the sensors can become misaligned. Also, wiring errors can be made, by factory workers, when the IC-chip testing apparatus is manufactured.
When any one of the above types of problems do occur, the resulting damage can be catastrophic because the motor needs to be quite powerful in order to squeeze all of the subassemblies together. Accordingly, a primary objective of the present invention is to provide an integrated circuit tester having a fail-safe mechanism for moving IC-chips which avoids the above problems.
In accordance with the present invention, an integrated circuit tester includes a fail-safe mechanism for moving an integrated circuit chip between an initial position where the integrated circuit chip is inserted into the tester, and a test position where the integrated circuit chip is actually tested. One preferred embodiment of this fail-safe mechanism for moving includes xe2x88x921) a motor; 2) a shaft, coupled to the motor, which has a threaded section that the motor rotates; 3) a threaded member which travels linearly along the threaded section of the shaft when the shaft is rotated by the motor; 4) a lifter arm, coupled to the threaded member, that moves between predetermined first and second positions in response to the linear travel of the threaded member; 5) a linkage means, coupled between the lifter arm and the integrated circuit chip, which places the integrated circuit chip at the initial position and the test position as the lifter arm moves to the first and second positions respectively; and, 6) the shaft has first and second unthreaded sections, adjacent to opposite ends of the threaded section, onto which the threaded member linearly travels and stops if the shaft fails to stop rotating when the lifter arm respectively reaches the first and second positions.
The above fail-safe mechanism can be used together with any electronic control circuit for automatically stopping the motor when the integrated circuit chip is at its initial position, or at its test position. If that electronic control circuit fails such that the motor continues to rotate the shaft when the chip reaches the initial position, or the test position, then no catastrophic damage to the integrated circuit tester will occur. That is because when the above failure occurs, the threaded member will linearly travel onto an unthreaded section of the shaft; and that will stop the lifter arm from moving.